NJU8715 -1- ver.2005-03-09 switching driver with regulator for class-d headphone amplifier general description the NJU8715 is a switching driver with regulator for class-d headphone amplifier. it incorporates an optimum regulator for the driver of headphone amplifier, class?d line amplifier and a beep amplifier. the NJU8715 converts 1bit digital signal of the pwm or the pdm to an analog signal output through a simple external lc low-pass filter. the NJU8715 provides a completed digital system and high power-efficiency with class-d operation. therefore, it is suitable for portable audio applications. features 2-channel 1bit audio signal input headphone output built-in class d line amplifier built-in regulator for driver beep function logic operating voltage 1.9 to 2.6v (v dd ) regulator operating voltage 4.0 to 5.75v (v g ) 1.9 to 4.0v (v reg ) c-mos technology package outline qfn28 block diagram package outline pin configuration NJU8715kn1 mode b beep in d in2 d in1 o beep1 v ss out 1 v ddo1 v rego v reg v cont v ref c fb v ddo2 en vg en reg en 2 en 1 v dd mck v ss c l c h v g nc o beep2 v ss out 2 28 1 beep in d in1 mc k v dd v ss d in2 out 1 v rego v reg o beep1 o beep2 c fb c h en 1 en reg en 2 en vg mode b v ref level shifter control logic regulato r v ss v ddo1 out 2 v ss v ddo2 v cont c l charge pum p v g pre driver level shifte r level shifte r level shifter level shifter pre driver pre driver pre driver hp amp hp amp line amp line amp beep amp beep amp preliminary
NJU8715 - 2 - - 2 - ver.2005-03-09 terminal description no. symbol i/o function 1 mode b i beep output level control terminal h: -39dbm, l: -48dbm the load of 16 ? (note.1) 2 beep in i beep signal input terminal 3 d in2 i audio signal input terminal 2 4 d in1 i audio signal input terminal 1 5 o beep1 o beep output terminal 1 6, 16, 22 v ss - power gnd: v ss =0v (note.2) 7 out 1 o output terminal 1 this terminal outputs d in1 terminal input data. 8 v ddo1 - driving power supply 1 9 v rego o regulator output terminal 10 v reg i regulator input terminal 11 v cont i regulator output voltage control terminal 12 v ref o reference voltage output terminal 13 c fb i regulator output voltage sense terminal 14 v ddo2 - driving power supply 2 15 out 2 o output terminal 2 this terminal outputs d in2 terminal input data. 17 o beep2 o beep output terminal 2 18 nc - non connection 19 v g - pre-driver power supply 20 c h - + capacitor connection terminal for the charge pump 21 c l - - capacitor connection terminal for the charge pump 23 mck i master clock input terminal the condition of the data input terminal is latched on the rising edge of this signal. 24 v dd - operation power supply 25 en 1 i hp/line/beep mode control terminal 1 (with pull-down resistor) 26 en 2 i hp/line/beep mode control terminal 2 (with pull-down resistor) 27 en reg i regulator enable terminal (with pull-down resistor) h : on, l : off 28 en vg i charging pump enable terminal (with pull-down resistor) h : on, l : off note.1) 0dbm ? 0.775vrms note.2) v ss (terminal no.6,16,22) should be connected at the nearest point to the ic. input terminal structure mck, d in1 , d in2 , beep in , mode b terminal v dd v ss input terminal v dd v ss input terminal en 1 , en 2 , en reg , en vg terminal
nju3555 NJU8715 -3- ver.2005-03-09 functional description (1) power supply v dd : power supply for input circuit and control logic. keep the input logic level less than v dd . v g : power supply for pre-driver which drives the transistor gates of output drivers. when envg=h, charge pump generates double the voltage of v dd , which is supplied to v g terminal through the inside. when envg=l, charge pump is halted, and v g terminal accepts the external power supply. v reg : power supply for built-in regulator. apply the required voltage with additional dropout voltage of regulator. by connecting v rego (regulator output) to v ddo1 , v ddo2 (driver power supply), the power is provided to the drivers. furthermore, the regulator output should be supplied to v ddo1 and v ddo2 by connecting de-coupling capacitor to get highly smoothed power supply. (2) regulator output voltage control terminal (v cont ) v cont is the control terminal for regulator output voltage. as v reg output voltage is variable from 0v by external dc voltage, driver output level can be used as sound volume. (3) regulator enable signal (en reg ) the regulator is halted at ?l? level, and works at ?h? level. (4) charging pump enable signal (en vg ) the charge pump is halted at ?l? level, and works at ?h? level. (5) hp/line/beep mode control terminal (en 1 / en 2 ) each mode can be selected by a combination setting of en 1 and en 2 . the following table shows each output condition of each mode. input output mode en 1 en 2 hp amp. line amp. beep amp. standby mode l l hiz hiz hiz line mode l h hiz active hiz hp mode h l active hiz hiz beep mode h h hiz hiz active (6) beep signal input (beep in ) (7) beep signal output (o beep1 / o beep2 ) beep signal is output in a square wave. (8) master clock (mck) master clock (mck) synchronizes the audio signal inputs(d in1 , d in2 ). the setup time and the hold time should be kept in the ac characteristics because d in1 and d in2 are latched on the rising edge of mck. during the standby condition, mck requires ?l? level to avoid unnecessary power consumption. in addition, mck requires jitter-free or fewer jitter because the jitter could lead to poor s/n ratio. (9) signal output ( out 1 / out 2 ) out 1 and out 2 terminals keep the hi-z condition if output voltage of v rego is lower than detection voltage. output signals are appeared as pwm signals through the use of v ddo1 and v ddo2 in the out 1 and out 2 terminals if the output voltage is over than detection voltage. output signals will be converted to analog signals via 2nd-order or higher lc filter.
NJU8715 - 4 - - 4 - ver.2005-03-09 power on/down sequence the pop-noise can be effectively suppressed with the following sequence when power on and down. (1) power on / power down sequence (en vg =h: using internal v g ) < power on sequence > 1) input the mck after the start-up of v dd . after of 100ms delay or more from mck input, set en vg at ?h? level. 2) set en seg at ?h? level after 5ms delay or more.(at 0.1 f for the charge pump and 1 f for the smoothing capacitor) 3) after setting en reg at ?h? level, input audio signals(d in1 , d in2 ). 4) set en 1 at ?h? level and en 2 at ?l? level after audio signal input. the audio signal input must be ?sound-less data? until v cont reaches a steady state. 5) v cont should be applied gradually to the target voltage. if the rising time of the application to the target v cont voltage is short, it may cause a pop-noise. < power down sequence > the sequence must be executed in inverse order of the power on sequence. * : do not set d in1 and d in2 at ?h? level before the start-up of v dd . high impedance en 2 d in1 , d in2 audio data v cont mc k sound-les data sound-less data out 1 , out 2 audio signal output high impedance en reg v g en 1 100ms or more 100ms or more v dd , v reg en vg undefined data* undefined data*
nju3555 NJU8715 -5- ver.2005-03-09 (2)power on / power down sequence(en vg =l, v g : externally applied) < power on sequence > 1) input the mck after the start-up of v dd . apply v g after the start-up v dd .(as shown in the following sequence, v g increases to v dd through a internal protection diode after v dd is turned on.) 2) set en reg at ?h? level after the start-up of v g . 3) after setting en reg at ?h? level, input audio signals(d in1 , d in2 ). 4) set en 1 at ?h? level and en 2 at ?l? level after audio signal input. the audio signal input must be ?sound-less data? until v cont reaches a steady state. 5) v cont should be applied gradually to the target voltage. if the rising time of the application to the target v cont voltage is short, it may cause a pop-noise. < power down sequence > the sequence must be executed in inverse order of the power on sequence. * : do not set d in1 and d in2 at ?h? level before the start-up of v dd . high impedance en 2 d in1 , d in2 audio data v cont mc k sound-less data sound-less data out 1 , out 2 audio signal output high impedance en reg v g en 1 100ms or more 100ms or more v dd , v reg en vg undefined data* undefined data*
NJU8715 - 6 - - 6 - ver.2005-03-09 absolute maximum ratings (ta=25 c) parameter symbol rating unit v dd -0.3 ~ +2.75 v v reg -0.3 ~ +5.5 v supply voltage v g v dd ~ +6.0 v input voltage vin -0.3 ~ v dd +0.3 v operating temperature ta -20 ~ +85 c storage temperature tstg -40 ~ +125 c power dissipation p d 640 mw note.3) the relations of v ddo1 ,v ddo2 nju3555 NJU8715 -7- ver.2005-03-09 electrical characteristics (1) dc characteristics (ta=25 c, v dd =2.0v, v ddo1 =v ddo2 =1.7v, v reg =2.15v, v ss =v sso =0.0v, load impedance=16 ? , f s =44.1khz, unless otherwise noted) parameter symbol conditions min typ max unit v dd supply voltage v dd 1.9 2.0 2.6 v v g supply voltage v g v g : externally applied 4.0 5.0 5.75 v hp driver high side resistance r hph out 1, 2 =v ddo1, 2 -0.1v - 1.2 2 ? hp driver low side resistance r hpl out 1, 2 =0.1v - 1.2 2 ? line driver high side resistance r lineh out 1, 2 =v ddo1, 2 -0.1v v ddo1, 2 =2.75v 7.7 11 14.3 ? line driver low side resistance r linel out 1, 2 =0.1v v ddo1, 2 =2.75v 7.7 11 14.3 ? v beepl mode b =l -50 (2.45) -48 (3.08) -46 (3.88) beep output voltage v beeph mode b =h -41 (6.91) -39 (8.70) -37 (10.95) dbm (mvrms) power supply current at standby i st standby mode stopping mck,d in1 ,d in2, beep in en reg =l - - 1 a i dd1 - 0.95 1.6 i reg1 using internal v g hp mode no-load operating, mck=256fs d in1 ,d in2 =16fs, en reg =h - 0.70 1.2 ma i dd2 - 0.05 0.10 i reg2 - 0.70 1.2 power supply current at operating (mute signal input) i g2 v g : externally applied, hp mode no-load operating, mck=256fs, d in1 ,d in2 =16fs,en reg =h v g =5v - 0.75 1.2 ma v ih 0.7v dd - v dd v digital input voltage v il mck, d in1 , d in2 beep in , mode b en 1 , en 2 , en reg , en vg 0 - 0.3 v dd v input leakage current i lk mck, d in1 , d in2 beep in , mode b - - 1 a pull-down resistance r pd en 1 , en 2 , en reg , en vg 150 300 450 k ?
NJU8715 - 8 - - 8 - ver.2005-03-09 (2) regulator characteristics (ta=25 c, v dd =2.0v, v ddo1 =v ddo2 =1.7v, v reg =2.15v, v ss =v sso =0.0v, load impedance=16 ? , f s =44.1khz, unless otherwise noted) parameter symbol conditions min typ max unit v regh hp mode 1.9 2.15 4.0 v input voltage v regl line mode 3.0 - 4.0 v v ddoh1 hp mode v cont =1.5v, v reg =2.5v 1.9 2.0 2.1 v v ddoh2 hp mode v cont =0.5v, v reg =2.5v 0.23 0.33 0.43 v v ddol1 line mode v cont =1.5v, v reg =3.5v 2.8 2.9 3.0 v output voltage v ddol2 line mode v cont =0.5v, v reg =3.5v 0.38 0.48 0.58 v output current i out 70 - - ma sink current i sink 60 - - ma dropout voltage ? v io iout=70ma v ddo1, 2 =1.7v - - 0.2 v ripple rejection rr vr=0.1vrms, iout=70ma fr=1khz 36 44 - db load regulation voltage v lr i rego =0 ~ 24.3marms - - 520 vrms residual voltage v min v cont =0.1v - - 10 mv v cont v cont 0 - v reg v the following figure shows a representative example of v cont versus v rego . at v cont =1.5v: v rego =2.0v(v reg =2.5v) in hp mode, v rego =2.9v(v reg =3.5v) in line mode. at v cont =0.5v: v rego =0.33v(v reg =2.5v) in hp mode, v rego =0.48v(v reg =3.5v) in line mode. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 line mode hp mode v cont (v) v r ego ( v )
nju3555 NJU8715 -9- ver.2005-03-09 (3) ac characteristics (ta=25 c, v dd =2.0v, v ddo1 =v ddo2 =1.7v, v reg =2.15v, v ss =v sso =0.0v, load impedance=16 ? , f s =44.1khz, unless otherwise noted) ? master clock parameter symbol conditions min typ max unit frequency f mcki 8 - 50 mhz pulse width (h) t mckh 8 - - ns pulse width (l) t mckl 8 - - ns ? digital audio data parameter symbol conditions min typ max unit d in1 , d in2 setup time t ds 5 - - ns d in1, d in2 hold time t dh 5 - - ns en 1 , en 2 , en reg , en vg , beep in , mode b rise time, fall time t er , t ef - - 50 ns t mckh mc k t mckl 0.7v dd 0.3v dd 0.7v dd 0.3v dd t er t ef en 1 , en 2 , en reg , en vg , beep in , mode b timing chart t ds t dh d in1 , d in2 mck, d in1 , d in2 timing chart 0.7v dd 0.3v dd
NJU8715 - 10 - - 10 - ver.2005-03-09 application circuit (1) using internal v g (en vg =h) regulator input NJU8715 v dd v ss v reg v ss v ss out 1 o beep1 mck d in1 d in2 beep in 2.2 f 2.2 f v dd c fb v rego v ddo1 v ddo2 v ref en reg en vg en 1 en 2 mode b c l c h v g head phone 16 ? 0.1 f 1 f 220 f 47 h 4.7k ? 220 f 0.22 ? 47 h 4.7k ? 220 f 0.22 f 1 f 1 f
nju3555 NJU8715 -11- ver.2005-03-09 (2) v g : externally applied (en vg =l) note.7) c h and c l pins must be opened when v g externally applied. note.8) de-coupling capacitors must be connected between each power supply pin and gnd pin. the capacitor value should be adjusted on the application circuit and the temperature. it may malfunction if capacity value is small. note.9) a large-capacitance for the de-coupling capacitors for headphone speaker is recommended to improve a low-frequency characteristics. in addition, a low-esr(equivalent series resistance) capacitor is recommened for high power efficiency. note.10) the above circuit shows only application example and does not guarantee the any electrical characteristics. therefore, please consider and check the circuit carefully to fit your application. 1 f v g regulator input NJU8715 v dd v ss v reg v ss v ss out 1 o beep1 mck d in1 d in2 beep in 2.2 f 2.2 f v dd c fb v rego v ddo1 v ddo2 v ref en reg en vg en 1 en 2 mode b c l c h v g 220 f out 2 o beep2 v cont v rego control signal 10 f 1 f 1 f head phone 16 ? 47 h 4.7k ? 220 f 0.22 ? 47 h 4.7k ? 220 f 0.22
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